soft-core
英 [ˈsɒft kɔː(r)]
美 [ˈsɔːft kɔːr]
adj. 软性色情的; (性描写等)隐晦的,含蓄的
牛津词典
adj.
- 软性色情的;(性描写等)隐晦的,含蓄的
showing or describing sexual activity without being too detailed or shocking
柯林斯词典
- (性描写)非赤裸裸的,较隐晦的
Soft-corepornography shows or describes sex, but not very violent or unpleasant sex, or not in a very detailed way.
双语例句
- With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
通过建立SDH芯片验证平台和SDH芯片测试平台,实现IP软核的功能仿真、时序仿真和芯片性能测试。 - The Nios ⅱ soft-core processor improve the integration of the system and is helpful to the miniaturization of instrument.
NiosⅡ软核处理器提高了系统的集成度,有利于系统的小型化,降低了成本。 - Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
详细设计了帧间解码IP软核,包括运动矢量生成模块、预测处理模块和插值模块。 - To solute the problem, the idea of kernel hardware design has been put forward. System architecture is divided into soft-core and hardcore. Hardcore will manage application tasks as a coprocessor to improve the real time of system.
针对实时性问题,提出将内核硬件化设计的思想,将系统的体系结构划分为软核和硬核,硬核作为协处理器管理应用任务,提高系统的实时性,使系统的性能得到明显的提高。 - Research and Design of Soft-core IP for AVS Inter Decoder
AVS帧间解码IP软核的研究与设计 - It inherits the hardcore, soft-core, DSP, memory, peripheral I/ O and programmable logic.
它继承了硬核、软核、DSP、存储器外围I∕O及可编程逻辑。 - In practice, the designer can use this soft-core as a communication module through the FPGA implementation or to quickly build a Field Bus communication system to realize flexible CAN bus interface solutions.
在实际应用中设计者可以将此软核作为通讯模块通过FPGA实现,或者快速搭建现场总线通信系统,实现灵活的CAN总线接口方案。 - The prototype designs with soft-core processors of Nios II in FPGA, improves the programmability of network processors.
网络处理器芯片原型采用NIOSii软核处理器在FPGA上实现,提高了网络处理器的可编程能力。 - I distinctly remember my high school self, wide-eyed, poring over the soft-core Starr report with friends.
我还清楚地记得高中时代的我,睁大了眼睛,和朋友们一起狼吞虎咽地读着《斯塔尔报告》(StarrReport)中那些香艳的内容。 - A 40Gb/ s switch IP soft-core with self-dependence intellectual property was realized.
形成了具有自主知识产权的40Gb/s交换IP软核。